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SpiNNaker: Fault tolerance in a power- and area- Constrained large-Scale neuromimetic architecture

机译:spiNNaker:功率和区域约束的大规模神经模拟架构中的容错

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摘要

SpiNNaker is a biologically-inspired massively-parallel computer designed to model up to a billion spiking neurons in real-time. A full-fledged implementation of a SpiNNaker system will comprise more than 105 integrated circuits (half of which are SDRAMs and half multi-core systems-on-chip). Given this scale, it is unavoidable that some components fail and, in consequence, fault-tolerance is a foundation of the system design. Although the target application can tolerate a certain, low level of failures, important efforts have been devoted to incorporate different techniques for fault tolerance. This paper is devoted to discussing how hardware and software mechanisms collaborate to make SpiNNaker operate properly even in the very likely scenario of component failures and how it can tolerate system-degradation levels well above those expected. © 2013 The Authors. Published by Elsevier B.V. All rights reserved.
机译:SpiNNaker是一台受生物学启发的大规模并行计算机,旨在实时建模多达十亿个尖峰神经元。 SpiNNaker系统的完整实现将包括105个以上的集成电路(其中一半是SDRAM,一半是多核片上系统)。在这种规模下,不可避免地会出现某些组件发生故障的情况,因此,容错是系统设计的基础。尽管目标应用程序可以容忍一定程度的低级别故障,但是已经投入了重要的努力来合并不同的技术以实现容错能力。本文致力于讨论即使在极有可能出现组件故障的情况下,硬件和软件机制如何协作以使SpiNNaker正常运行,以及它如何能够承受远高于预期的系统降级水平。 ©2013作者。由Elsevier B.V.发布。保留所有权利。

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